Real Space Transfer (RST) describes the process in which carriers in a narrow semiconductor layer, accelerated by an electric field parallel to the layer acquire high average energy and become hot carriers. These carriers surmount or can tunnel through an energy barrier into adjacent layers. This redistribution of carriers between parallel layers having different mobility leads to negative differential resistance (NDR). NDR is the result of the real space transfer of hot carriers' from a hot channel to a cooler channel, thus reducing the source-drain current for an increasing electric field. In gallium arsenide and silicon germanium based heterojunctions, relatively low heterojunction barriers make it possible for carriers in the channel to be accelerated by the source/drain field of a typical FET structure. These carriers may be accelerated to energies high enough to permit real-space transfer through the barrier (tunneling) or over the barrier. This effect is exploited in a variety of structures to include real-space transfer diodes and three and four terminal devices known as negative resistance field effect transistors (NERFET). In NERFETs, electrons heated in the channel of a heterojunction field effect transistor are collected in the gate or back gate electrode (thus the transport is perpendicular to the channel by virtue of RST).
FIG. 4 shows a typical charge injection transistor (CHINT). The basic device has a source 401, a drain 402 and a collector 403. In the illustrative CHINT of FIG. 4, the collector layer is Si.sub.x Ge.sub.1-x, the barrier is Si and the channel is Si.sub.x Ge.sub.1-x, although III-V based heterostructure CHINT's function in a similar manner as described herein. In operation, parallel transport is from the source to the drain of the device. When the applied electric field (bias) is increased sufficiently, carriers in the top layer 404 are heated by the source-drain field causing most not to reach the drain 402. Instead, they are injected over the barrier layer 405 into the collector layer 406 through RST. Si/Si-Ge heterojunctions have also been explored for use in RST based devices for high speed logic and oscillator applications. While silicon/silicon germanium heterostructures are of practical interest because of possibilities of integration of charge injection devices into standard CMOS logic and other devices, there are clearly drawbacks to RST devices based on silicon germnanium. To this end, while silicon germanium is more readily integrated into current CMOS processing sequences, fabrication complexity issues still remain with silicon germanium. Furthermore, the potential barrier between silicon and silicon germanium is on the order of 0.1 eV; and since almost all the bandgap discontinuity between the strained Si.sub.x Ge.sub.1-x channel and the Si barrier falls into the valence band, the devices based on RST in SiGe rely on hot holes as the carriers. This is less desirable than the case where the carriers are electrons as the mobility of holes is lower than that of electrons.
Charge injection transistors, have been fabricated using III-V heterostructures to include GaAs/AlGaAs and InGaAs/InAlAs heterostructures. While there are certain benefits achieved through the III-V based heterojunctions there are drawbacks to such structures. Gallium arsenide structures are generally more expensive and more difficult to fabricate than their silicon counterparts due to the complexity of fabrication steps as well as materials required. Furthermore, while AlGaAs/GaAs and InGaAs/InAlAs heterojunctions can be used to form an RST based devices, the potential barrier between the two layers is on the order of 0.3 eV and 0.5 eV, respectively. Further details of Si/SiGe and III-V based CHINT devices can be found in Functional Devices Based on Real Space Transfer in Si/SiGe Structure, IEEE Transcations on Electron Devices, Vol 43, No. 10, October 1996, to Mastrapasqua, et al, p 1671-1677 and High Transconductance and Large Peak-to-Valley Ratio of Negative Differential Conductance in Three Terminal InGaAs/InAlAs Real-Space Transfer Devices, Appled Physics Letters Vol. 57, 1990, to Mensz, et al, respectively. The disclosures of these articles are specifically incorporated herein by reference.
Accordingly, leakage current issues tend to plague the gallium arsenide based devices. Thus, the adaptability of gallium arsenide and silicon germanium based heterojunction RST devices is suspect because of the attendant problems associated with fabrication, as well as mobility issues and leakage current issues. Accordingly, what is needed is a structure which can be readily incorporated into silicon MOS process sequences, while improving the performance of RST based devices.